(1) Field of the Invention
The present invention relates generally to electronic oscillators usable as clock generators and in particular to improved crystal resonator oscillators, thin-film resonator or micro electromechanical resonator oscillators, realized with monolithic integrated-circuit technologies, where one chip solutions include automatic amplitude control and biasing to accommodate a highly accurate frequency-generation exhibiting low phase noise and stable amplitudes up to higher frequencies.
(2) Description of the Prior Art
Crystal oscillators in monolithic integrated circuit technology are developed using Pierce oscillator or three-point oscillator circuit schemes, where the frequency determining resonator is working in a resonance mode, where the equivalent reactance is inductive. Realized with quartz crystals as resonators normally phase noise is considered sufficiently good at frequency offsets not too far away from the oscillator carrier signal. It would be advantageous to extend the operating range whilst maintaining a good phase noise behavior at farer away offsets.
Crystal-controlled oscillators have been in use for decades in electronic systems as frequency references; but such oscillators have mostly been implemented using bi-polar transistors as active elements. However, the dominant technology for the fabrication of most integrated circuits today is CMOS and design techniques for highly stable crystal oscillators in this technology are less well known, especially when it comes to frequencies of about 100 MHz, as necessary for modern communication applications.
In the prior art, there are different technical approaches for achieving the goals of good tuneability over wider ranges and low phase noise. These crystal oscillator arrangements always include a piezo-electric, e.g. quartz, crystal and drive current means therefore. Unfortunately, these approaches are somewhat expensive, both in terms of technical complexity (e.g. differential push-pull or balanced bridge structures, extra filter or tank circuits, sophisticated temperature compensation or gain control circuits, amplitude peak detectors etc.) and—hence—commercial costs. It would be advantageous to reduce both expenses. This is achieved by using an oscillator circuit working with a crystal in inductive resonance mode, as three-point oscillator derived from the Pierce oscillator. Using the intrinsic advantages of that solution—as described later on in every detail—the circuit of the invention is realized with standard CMOS technology at low cost.
Preferred prior art realizations are implementing such related crystal oscillator circuits in single chip or multiple chip solutions as integrated circuits. The large chip areas needed and consequently the high costs are the main disadvantages of these prior art solutions. It is therefore a challenge for the designer of such devices and circuits to achieve a high-quality but also low-cost solution.
Several prior art inventions referring to such solutions describe related methods, devices and circuits, and there are also several such solutions available with various patents referring to comparable approaches, out of which some are listed in the following:
U.S. Pat. No. 5,606,295 (to Ohara, et al.) describes crystal oscillator circuits, wherein a one pin on-chip crystal oscillator circuit and a method of operating that oscillator are provided. The oscillator makes use of the gate-source capacitance of a MOS transistor to provide capacitance which would otherwise need to be provided by one of two oscillator capacitors. The MOS transistor is provided with a floating well by coupling its body to its source, so that the gate-source capacitance does not change substantially when the transistor is turned off. In another aspect of the invention, the MOS transistor is provided with a floating well using a parallel combination of MOS transistor elements, so as to minimize the coupling resistance of the MOS transistor to other elements of the circuit. In another aspect of the invention, the MOS transistor is coupled to a simulated inductive circuit for assuring that the impedance of the two passive oscillator components, normally capacitors, is inductive (will not oscillate) at frequencies near the fundamental frequency of the crystal and capacitive (will oscillate) at frequencies near the third harmonic of the crystal. In another aspect of the invention, the MOS transistor is coupled to a circuit for setting its transconductance by reference to an external component.
U.S. Pat. No. 5,621,361 (to Adduci) discloses a one-pin integrated crystal oscillator, wherein said one-pin integrated crystal oscillator in a Colpitts configuration employs a differential amplifier, provided with a feedback network, as an input gain stage. This achieves an enhanced stability and independence from temperature variation, a high Q figure, and a short start-up with a relatively small area of integration.
U.S. Pat. No. 6,028,491 (to Stanchak et al.) shows a crystal oscillator with controlled duty-cycle wherein an oscillator circuit having a first node oscillating with a first indeterminate duty-cycle and having a second node oscillating with a predetermined second duty-cycle. Both nodes oscillate at similar frequencies. A variable current source and a switch are coupled in series between Vcc and ground with the output of the variable current source being the second node. The first node controls the switch, which is closed when the first node is at a first logic state and is opened when it is at a second logic state. During each cycle, a monitoring circuit measures the time span that the first node is at the first logic state and adjusts the magnitude of the variable current source to make it directly proportional to the measured time span. By adjusting the variable current source, the second node can be made to reach a desired voltage level in a desired amount of time during each cycle. In a second embodiment, a current limiting transistor is inserted between the second node and the switch. The current limiting transistor is controlled by the monitoring circuit and is made to reduce the influence of the switch on the second node as the duty-cycle of the first node approaches the predetermined second duty-cycle.
The related literature sees two relevant papers. In the paper from Robert G. Meyer et al.—cited here as [Meyer, R.G. Soo, D. C.-F. “MOS Crystal Oscillator Design,” IEEE Journal of Solid-State Circuits, Vol. SC-15, No. 2, April 1980, pp. 222–228] first, describing the operation of MOS crystal oscillators as investigated assuming near-sinusoidal AC voltages at gate and drain, wherein is shown that the circuit operation depends basically on only two normalized parameters. Computer solutions are used to produce a series of normalized curves allowing oscillator design for prescribed start-up conditions, steady-state amplitude, and operating current. The theoretical predictions therein agree closely with measurements on sample circuits. The second paper from Eric A. Vittoz et al. cited here as [Vittoz, E. A. Degrauwe, M. G. R. & Bitz, S. “High-Performance Crystal Oscillator Circuits: Theory and Application,” IEEE Journal of Solid State Circuits, Vol. SC-23, No. 3, June 1988, pp. 774–783] presents a general theory that allows the accurate linear and nonlinear analysis of any crystal oscillator circuit. It is based on the high Q of the resonator and on a very few nonlimiting assumptions. The special case of the three-point oscillator, that includes Pierce and one-pin circuits, is analyzed in more detail. A clear insight into the linear behavior, including the effect of losses, is obtained by means of the circular locus of the circuit impedance. A basic condition for oscillation and simple analytic expressions are derived in the lossless case for frequency pulling, critical transconductance, and start-up time constant. The effects of nonlinearities on amplitude and on frequency stability are analyzed. As an application, a 2-MHz CMOS oscillator which uses amplitude stabilization to minimize power consumption and to eliminate the effects of nonlinearities on frequency is described. The chip, implemented in a 3-μm p-well low-voltage process, includes a three-stage frequency divider and consumes 0.9 μA at 1.5 V. The measured frequency stability is 0.05 p.p.m./V in the range 1.1–5 V of supply voltage. Temperature effect on the circuit itself is less than 0.1 p.p.m. from −10 to +60° C.
The basic three-point oscillator circuit is shown in FIG. 1A prior art in form of a simplified circuit diagram (i.e. without power supply and ground connections) with one Field Effect Transistor (FET) M1 with conductance gm as the active i.e. amplifying component and named as such also as basic active component, connected at said three nodes (1, 2 & 3 shown encircled) to a resonator element (with its equivalence elements: resistance Rs, capacitance Cs and inductance Ls and a parasitic capacitance Cp); the FET being current-voltage biased by a resistive component Rbias and all embedded within a capacitance PI-configuration, consisting of two capacitors C1 and C2. FIG. 1B prior art on the left side redraws this configuration somewhat more generally, now introducing three impedances Z1, Z2 and Z3 as substitution for Cp, Rbias as well as C1 and C2 from FIG. 1A prior art, it shall be pointed out, that the resonator can now be understood as virtually terminated by a complex impedance Zc. On the right side an electrically equivalent circuit is given, with Rs, Cs and Ls from the resonator equivalence diagram and these virtual complex impedance Zc, represented by its real and imaginary parts Re(Zc)=Cosc and Im(Zc)=Rosc. This virtual impedance Zc replaces the whole active driving part of the oscillator and by virtue of power matching, ruling that the impedance Zc has to be conjugated complex i.e. the resonator beeing essentially inductive we need an essentially capacitive impedance Zc, such as it is depicted in FIG. 1B prior art to the utmost right with a serial circuit of Rosc and Cosc, therefore obligatory incorporating the effects of the load capacitors C1 and C2. Some further aspects for design and development of oscillator Integrated Circuits (IC) shall be noted here. Today's ICs are complete electronic systems often requiring a crystal oscillator to generate an accurate clock signal. Recent advances in technology allow for ever increasing clock frequencies. The standard configuration for clock generators is a Pierce oscillator that has the crystal and its load capacitors connected between two pins of the IC. With the trend to minimize the number of external components the load capacitors are sometimes integrated. In order to be able to trim the resonance frequency these load capacitors can then be implemented as capacitor banks switched by digital circuitry. In a Pierce oscillator both capacitors are referring to ground facilitating the use of MOS gate capacitances and thereby greatly reducing the chip area. Still due to the limited number of pins on an IC-package it is desirable to have the same function with a single pin and the crystal referring to ground. Several one pin oscillators have been reported, but they all need at least one floating capacitor. This leads to large chip area or expensive process options and difficulties with respect to tuning by means of switched capacitor banks. Most one pin oscillators are a variant of the three point oscillator of which the basic oscillator block is depicted in FIG. 1A prior art, wherein the crystal is represented as a series resonant branch Rs, Cs and Ls and said parasitic lead capacitor Cp. If node 1 (encircled) or 2 (encircled) is set to ground and the other nodes are properly biased the crystal can be externally grounded. This results in a one pin oscillator. Setting node 3 (encircled) to ground instead gives a Pierce oscillator. C1 and C2 are the load capacitors of which the series value should equal the crystals specific load capacitance to obtain the nominal crystal frequency. The importance of these oscillator circuits for modern IC-design is therefore clearly explained; for oscillators of the three-point, Pierce and one-pin type likewise.
Although these patents and papers describe circuits and/or methods close to the field of the invention they differ in essential features from the method, the system and especially the circuit introduced here.